Extra+Credit

code Vdd   Vdd    0    2.5
 * EE 307 CMOS AND Gate Project Winter 2008
 * Rails

VI1 Vin1 0 PULSE (2.5 0 0 0.5n 0.5n 5n 10n) VI2 Vin2 0 PULSE (2.5 0 0 0.5n 0.5n 10n 20n) VI3 Vin3 0 PULSE (2.5 0 0 0.5n 0.5n 20n 40n) VI4 Vin4 0 PULSE (2.5 0 0 0.5n 0.5n 40n 80n) VI5 Vin5 0 PULSE (2.5 0 0 0.5n 0.5n 80n 160n) VI6 Vin6 0 PULSE (2.5 0 0 0.5n 0.5n 160n 320n) VI7 Vin7 0 PULSE (2.5 0 0 0.5n 0.5n 320n 640n) VI8 Vin8 0 PULSE (2.5 0 0 0.5n 0.5n 640n 1280n)

Xupper Vin1 Vin2 Vin3 Vin4 Upper_out Vdd MODNAND4 Xlower Vin5 Vin6 Vin7 Vin8 Lower_out Vdd MODNAND4 Xnor   Upper_out Lower_out 52 Vdd MODNOR2x4 Cout2  52   0     1p
 * Medium Two-Level AND Gate Figures 2,5
 * All inputs (1-8) tied together
 * All inputs (1-8) tied together

.SUBCKT MODNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.75u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.00u L=0.25u MN3   3    In3   2   0     CMOSN W=1.25u L=0.25u MN2   2    In2   1   0     CMOSN W=1.50u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; MODNAND4
 * Subcircuit Definitions                                  *
 * Subcircuit Definitions                                  *

.SUBCKT MODNOR2x4 In1 In2 Out Vdd MP1   Out   In1   1   Vdd    CMOSP W=8u L=0.25u MP2     1   In2 Vdd   Vdd    CMOSP W=8u L=0.25u MN2   Out   In2   0     0    CMOSN W=2u L=0.25u MN1   Out   In1   0     0    CMOSN W=2u L=0.25u .ENDS ; NOR2x4


 * End Subcircuit Definitions                              *
 * End Subcircuit Definitions                              *

.TRAN   20n 1280n 0 1.28n .probe .OP
 * print_step final_time (results_delay) (step_ceiling)
 * The last two parameters are officially optional,
 * but I recommend that you specify a step_ceiling no
 * greater than the smaller of final_time/1000 or (rise or fall time)/10.
 * .DC Vin 0 2.5 0.001

.MODEL CMOSN NMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.4317311 + PHI    = 0.7             VTO    = 0.4238252       DELTA  = 0 + UO     = 425.6466519     ETA    = 0               THETA  = 0.1754054 + KP     = 2.501048E-4     VMAX   = 8.287851E4      KAPPA  = 0.1686779 + RSH    = 4.062439E-3     NFS    = 1E12            TPG    = 1 + XJ     = 3E-7            LD     = 3.162278E-11    WD     = 1.232881E-8 + CGDO   = 6.2E-10         CGSO   = 6.2E-10         CGBO   = 1E-10 + CJ     = 1.81211E-3      PB     = 0.5             MJ     = 0.3282553 + CJSW   = 5.341337E-10    MJSW   = 0.5             )
 * FET Model Parameters                                                     *
 * From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt    *
 * TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring   *
 * DEV: N3740/10    * Temp= 27                                              *
 * DEV: N3740/10    * Temp= 27                                              *

.MODEL CMOSP PMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.6348369 + PHI    = 0.7             VTO    = -0.5536085      DELTA  = 0 + UO     = 250             ETA    = 0               THETA  = 0.1573195 + KP     = 5.194153E-5     VMAX   = 2.295325E5      KAPPA  = 0.7448494 + RSH    = 30.0776952      NFS    = 1E12            TPG    = -1 + XJ     = 2E-7            LD     = 9.968346E-13    WD     = 5.475113E-9 + CGDO   = 6.66E-10        CGSO   = 6.66E-10        CGBO   = 1E-10 + CJ     = 1.893569E-3     PB     = 0.9906013       MJ     = 0.4664287 + CJSW   = 3.625544E-10    MJSW   = 0.5             )

.end code







As seen from the simulations, the power dissipation of the custom gate running with a 100 MHz 8-bit counter as the input (as opposed to the input as the same 100 MHz square wave applied to each input) is nearly zero. When the inputs were all tied together, and a high input is applied, the maximum amount of current the circuit can draw is drawn. As a result, maximum power dissipation is seen.

In the case where an 8-bit counter is applied as the input, the different inputs are either high or low, but not all high simultaneously. More specifically, input 1 of the custom gate switches between high and low throughout the transient simulation—but as a complementary input 8 is low for half of the time range of the transient analysis. It thus follows that the 8-bit counter provides a power dissipation of nearly zero watts.