Summary

Summary of the CMOS AND Gates Analysis (8-input AND gate):
(ns*mW*µm²) || 36.78 || 12.00 || 35.53 || 7.600 || NMOS: W= 4 L=.25 || For NAND4 gates: PMOS: W= .25 L=.25 NMOS: W= 4 L=.25
 * || Big Two-Level || Medium Two-Level || Four Level || Optimized Med. Two-Level ||
 * Speed (ns) || 1.428 || 1.255 || 0.7998 || 1.193 ||
 * Avg. Power (mW) || 0.7465 || 0.7080 || 1.154 || 0.6870 ||
 * Area (µm²) || 34.5 || 13.5 || 38.5 || 9.25 ||
 * Figure of Merit
 * Trans. Sizes (µm) || PMOS: W=.25 L=.25

For NOR2x4 Gate: PMOS: W= 8 L=.25 NMOS: W=2 L=.25 || For NAND2 gates: PMOS: W=.25 L=.25 NMOS: W=1 L=.25

For NOR2x4 Gate: PMOS: W=8 L= .25 NMOS: W=2 L= .25

For NAND2x16 gate: PMOS: W=4 L=.25 NMOS: W=16 L=.25 || For NAND4 gates: PMOS: W=.75 L=.25 NMOS4: W=1 L=25 NMOS3: W=1.25 L=.25 NMOS2: W=1.5 L=.25 NMOS1: W=1.75 L=.25

For NOR2x4 Gate: PMOS: W=8 L=.25 NMOS: W=2 L=.25 || Click here to see voltage and power characteristics.

Click here to see circuit definitions.

Click here to see how these figures were found.