Methods

Propagation Delay
By definition, the time it takes for the output voltage to react to changes to the input voltage. We measure this by finding the time starting where the input voltage reaches the midpoint of the total voltage (1.25V) and ending where the output voltage reaches the midpoint. This is done for both rise and fall phases and then averaged to find the total propagation delay.

Power
The average power dissipation is found by taking into account the input, output, and supply voltages/currents in each gate. We then let the simulation run until the average power levels out. The following is used in PSpice: code AVG(-V(Vdd)*I(Vdd)-I(Vin)*V(Vin1)+V(52)* I(Cout2))

code

Area
Depending on the circuit, different transistors and sizes are used. Detailed circuit info can be found here.

Design Method
1. After the comparison of the three circuits, we found that the medium two-level circuit has significantly low FOM. As a result, we decided to optimize this medium two-level circuit for our custom AND gate design.

2. Due to the lower carrier mobility of holes, PMOS stack series is slower than an NMOS stack. Therefore, NAND implementation is more preferable in a fast circuit design than NOR implementation. Our first attempt is to replace the 2-input NOR gate with three inverters and a 2-input NAND. However, under 1MHz, it required very strong PMOS pull-up transistors in the three inverters for rail-to-rail logics. This means that the size of three inverters will have to be big. At the end, this attempt didn’t decrease the FOM due to the increase of area compared to the original medium two-level circuit.

3. The other way to optimize the original circuit is to adjust the W/L ratio of the NAND gate. Using the MoHAT circuit analysis as following, we can see how the effect of W/L ratio can affect the VTC [1]. To simplify the analysis, we used a two-input NAND gate instead of the four-input NAND gate.

To calculate the gate threshold voltage: Vin = Vout = VM Hypothesis: MP1, MP3, MN2 Saturation and MN1 Linear
 * Assume both the PMOS and NMOS devices have the same conduction parameter kN and kP. Ignore the body effect of MN2 for simplification.

Analysis: With current through SAT MN1 and LIN MN2 (when Vin = Vout = VM), we can find the current through the NMOS: IDN = kN(VM – VDS1 – VTN)2 (1) IDN = kN[2(VM – VTN)VDS1 – VDS12] (2) Also, current goes through the MP1 and MP2 with the current relationship: 2IDP = IDN (3) And the current through the SAT MP1 and MP2 is IDP = kp(VDD – VM + VTP)^2 (4) Combining equation (1),(2),(3) and (4), we have



The resulting equation for VM shows that the ratio of kp/kN can directly affect the value of VM. Meanwhile, the W/L of the transistors affect the ratio of kP/kN according to the relationship:



Assume VTN = 0.4238, VTP = - 0.5536, µP/ µN = 4.82 and VDD = 2.5V First with (W/L)p = 1 and (W/L)N = 16

Test: MP1, MP3, MN2 Saturation and MN1 Linear (Check) Then, with (W/L)p = 3.0 and (W/L)N = 7.0, we have VM = 1.553V Test: MP1, MP3, MN2 Saturation and MN1 Linear (Check) || ||

4. As seen in the MoHAT analysis, by increasing the ratio of (W/L)P and (W/L­)N, we can increase the gate threshold voltage VM. As long as we maintained the noise margin, larger VM is desirable because large VM increase the current flow during the logic switch. For CMOS gate with, this means a better propagation delay and faster circuit. 5. Based on the previous analysis, we increased the ratio of (W/L)P and (W/L)N of the original circuit and also decreased the size of the NMOS significantly. Table I shows the result of the adjustment (the two Columns for the Original NAND gate and Small NAND gate). As expected, the value of VM increased from 0.806V to 1.303V whereas the VTC shifted to the right in Figure 1. Also, the noise margin and transition width were within reasonable range.

6. To further improve our custom NAND gate, we applied the transistor sizing technique to modify the W/L ratio for the NMOS. The progressive sizing technique entails that the pull up circuit elements (PMOS) all have the same W/L ratio. The pull down circuit elements (NMOS) get increasingly larger as you move closer to ground. The reason for this is that each NMOS must be able to carry the discharge current of the NMOS located in between itself and the output. As you move closer to ground, there is more discharge current to carry; therefore, a larger NMOS is appropriate. This sizing technique also keeps the diffusion capacitance contribution to the output capacitor small. With PGate = PDC + PAC = fCLVDD2 for CMOS gate, reducing CL means the reduction of both propagation delay and power dissipation.

7. Going off this theory, we decreased the size of the first NMOS to have a W/L ratio of 1µ/.25µ. From there we added 0.25µ to the width with each NMOS until ground. The four values were now 1µ/.25µ, 1.25µ/.25µ, 1.5µ/.25µ, 1.75µ/.25µ. Another important feature to consider is the size of the PMOS, although we did want to keep them all at the same ratio, we decided to increase their size for provide for a stronger PMOS and larger ratio of (W/L)P over (W/L)N. We increased it to .75µ/.25µ

Table I also shows the comparison between the small NAND gate and the Progressive NAND gate. The progressive sizing technique further increased our VM from 1.303V to 1.387V while maintaining reasonable noise margin. In Figure 1, the VTC shifted further to the right.

Table I: the comparison between different 4-input NAND Gate with different W/L ratio configuration. ||< Small NAND Gate ||< Progressive NAND || PMOS: W= .25 L=.25 NMOS: W= 4 L=.25 ||< PMOS: W=.75 L=.25 NMOS: W=1.75 L=.25
 * < ||< Original NAND Gate
 * < VIH ||< 0.9080 ||< 1.536 ||< 1.634 ||
 * < VIL ||< 0.5400 ||< 1.136 ||< 1.240 ||
 * < VM ||< 0.8060 ||< 1.303 ||< 1.387 ||
 * < NMH ||< 1.592 ||< 0.9644 ||< 0.8660 ||
 * < NML ||< 0.5400 ||< 1.136 ||< 1.240 ||
 * < Transition Width ||< 0.368 ||< 0.400 ||< 0.394 ||

||< PMOS: W=.75 L=.25 NMOS4: W=1 L=25 NMOS3: W=1.25 L=.25 NMOS2: W=1.5 L=.25 NMOS1: W=1.75 L=.25 ||
 * < (W/L)p ||< 1.0 ||< 3.0 ||< 3.0 ||
 * < (W/L)N ||< 16.0 ||< 7.0 ||< 4.0 / 5.0 / 6.0/ 7.0 ||
 * < Size ||< 5.0 ||< 2.5 ||< 2.125 ||



7. Finally, we m odified the original medium two level AND gate design with our two custom 4-input NAND gate design. Through analysis of the graphs created, we found a new **average propagation delay of 1.1925ns.**

8. We also measured the average power dissipation over a significant amount of time. Using the PSpice cursors on the following graph, we found **PD to be .687mW.**

9. The area of the circuit will be the area of each gate added together as follows:

2 NAND gates (4 PMOS and 4 NMOS each) Total are for both NAND gates is 2(2.125) = 4.25um²
 * || W (um) || L (um) || Area (um²) ||
 * PMOS || .75 || .25 || .1875 ||
 * NMOS4 || 1 || .25 || .25 ||
 * NMOS3 || 1.25 || .25 || .3125 ||
 * NMOS2 || 1.5 || .25 || .375 ||
 * NMOS1 || 1.75 || .25 || .4375 ||

Total area for NOR gate is 2(2.5) = 5um² Total area for entire circuit is 4.25 + 5 = 9.25um²
 * || W (um) || L (um) || Area (um²) ||
 * PMOS || 8 || .25 || 2 ||
 * NMOS || 2 || .25 || .5 ||

9. Using these three values (prop delay, average power and area) we can solve for the figure of merit. 1.1965ns x 0.687mW x 9.25um² = 7.600
 * Figure of Merit = Prop Delay x Area x Avg Power**

This value is 35% better than the original circuit which had a FOM of 12.00

10. Also, we measured the noise margin for the custom circuit and it meets the requirement of at least 0.25V.