Circuits

Analysis Circuit Definitions
 code MP1   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP2   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP3   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP4   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP5   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP6   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP7   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MP8   Vdd Vin1 18 Vdd  CMOSP W=0.25u L=0.25u MN8   18  Vin1 17   0  CMOSN W=16u L=0.25u MN7   17  Vin1 16   0  CMOSN W=16u L=0.25u MN6   16  Vin1 15   0  CMOSN W=16u L=0.25u MN5   15  Vin1 14   0  CMOSN W=16u L=0.25u MN4   14  Vin1 13   0  CMOSN W=16u L=0.25u MN3   13  Vin1 12   0  CMOSN W=16u L=0.25u MN2   12  Vin1 11   0  CMOSN W=16u L=0.25u MN1   11  Vin1 0    0  CMOSN W=16u L=0.25u MP9   51   18  Vdd Vdd  CMOSP W=4u L=0.25u MN9   51   18    0   0  CMOSN W=4u L=0.25u
 * ====Big two-level AND Gate==== ||  [[image:big.JPG]]
 * Big Two-Level AND Gate Figures 1,4,7                    *
 * Big NAND Gate with all inputs (1-8) tied together       *
 * Big NAND Gate with all inputs (1-8) tied together       *
 * Inverting buffer to output

Cout1   51   0     1p code ||  || code Xupper Vin1 Vin1 Vin1 Vin1 Upper_out Vdd NAND4 Xlower Vin1 Vin1 Vin1 Vin1 Lower_out Vdd NAND4 Xnor   Upper_out Lower_out 52 Vdd NOR2x4 Cout2  52   0     1p code || code X1Nand      Vin1 Vin1 X1Nand_out Vdd NAND2 X2Nand      Vin1 Vin1 X2Nand_out Vdd NAND2 X3Nand      Vin1 Vin1 X3Nand_out Vdd NAND2 X4Nand      Vin1 Vin1 X4Nand_out Vdd NAND2 X1Nor       X1Nand_out X2Nand_out X1Nor_out Vdd NOR2x4 X2Nor       X3Nand_out X4Nand_out X2Nor_out Vdd NOR2x4 X1Nand2x16  X1Nor_out X2Nor_out NAND2_out Vdd NAND2x16
 * ====Medium two-level AND Gate==== |||| [[image:medium.JPG]]
 * Medium Two-Level AND Gate Figures 2,5                   *
 * All inputs (1-8) tied together                          *
 * All inputs (1-8) tied together                          *
 * ====Four-level AND Gate==== |||| [[image:four.JPG width="563" height="451"]]
 * Four-Level AND Gate Figures 3,6                         *
 * All inputs (1-8) tied together                          *
 * All inputs (1-8) tied together                          *

MP53   53  NAND2_out  Vdd Vdd    CMOSP W=32u L=0.25u MN53   53  NAND2_out  0   0      CMOSN W=32u L=0.25u Cout3  53   0     1p code || code Xupper Vin1 Vin1 Vin1 Vin1 Upper_out Vdd MODNAND4 Xlower Vin1 Vin1 Vin1 Vin1 Lower_out Vdd MODNAND4 Xnor   Upper_out Lower_out 52 Vdd MODNOR2x4 Cout2  52   0     1p code ||  ||
 * ====Modified Medium Two-Level AND Gate==== || [[image:modmed.jpg]]
 * Medium Two-Level AND Gate Figures 2,5
 * All inputs (1-8) tied together
 * All inputs (1-8) tied together



Circuit Components

 * [[image:nand4.JPG]]

|| code .SUBCKT NAND4 In1 In2 In3 In4 Out Vdd MP1 Out In1 Vdd Vdd CMOSP W=0.25u L=0.25u MP2 Out In2 Vdd Vdd CMOSP W=0.25u L=0.25u MP3 Out In3 Vdd Vdd CMOSP W=0.25u L=0.25u MP4 Out In4 Vdd Vdd CMOSP W=0.25u L=0.25u MN4 Out In4 3 0 CMOSN W=4u L=0.25u MN3 3 In3 2 0 CMOSN W=4u L=0.25u MN2 2 In2 1 0 CMOSN W=4u L=0.25u MN1 1 In1 0 0 CMOSN W=4u L=0.25u .ENDS ; NAND4

.SUBCKT MODNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.75u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.00u L=0.25u MN3   3    In3   2   0     CMOSN W=1.25u L=0.25u MN2   2    In2   1   0     CMOSN W=1.50u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; MODNAND4

code || ||
 * **NAND4, MODNAND4 Subcircuit** || Note: This circuit has bigger NMOS than PMOS
 * [[image:nor2.JPG]]
 * [[image:nor2.JPG]]

|| code .SUBCKT NOR2x4 In1 In2 Out Vdd MP1   Out  In1   1   Vdd    CMOSP W=8u L=0.25u MP2     1  In2 Vdd   Vdd    CMOSP W=8u L=0.25u MN2   Out  In2   0     0    CMOSN W=2u L=0.25u MN1   Out  In1   0     0    CMOSN W=2u L=0.25u .ENDS ; NOR2x4

.SUBCKT MODNOR2x4 In1 In2 Out Vdd MP1   Out   In1   1   Vdd    CMOSP W=8u L=0.25u MP2     1   In2 Vdd   Vdd    CMOSP W=8u L=0.25u MN2   Out   In2   0     0    CMOSN W=2u L=0.25u MN1   Out   In1   0     0    CMOSN W=2u L=0.25u .ENDS ; NOR2x4 code || || code .SUBCKT NAND2x16 In1 In2 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=4u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=4u L=0.25u MN2   Out  In2   1   0     CMOSN W=16u L=0.25u MN1     1  In1   0   0     CMOSN W=16u L=0.25u .ENDS ; NAND2x16
 * **NOR2x4, MODNOR2x4 Subcircuit** || Note: This circuit has bigger PMOS than NMOS
 * [[image:nand2.JPG]] || 
 * [[image:nand2.JPG]] || 

.SUBCKT NAND2 In1 In2 Out Vdd MP1   Out  In1 Vdd Vdd   CMOSP W=0.25u L=0.25u MP2   Out  In2 Vdd Vdd   CMOSP W=0.25u L=0.25u MN2   Out  In2   1   0   CMOSN W=1u L=0.25u MN1     1  In1   0   0   CMOSN W=1u L=0.25u .ENDS ; NAND2

code || ||
 * **NAND2, NAND2x16Subcircuits** || Note: The NAND2 is 16 times small than the NAND2x16

PSpice Code for NAND Gate Design Comparison (Original NAND Gate, Smaller NAND Gate and the NAND Gate with Progressive sizing).
code Vdd   Vdd    0    2.5
 * EE 307 CMOS AND Gate Project Winter 2008
 * Rails

Vin   Vin1   0    ;PULSE (0 2.5 0 0.5n 0.5n 5n 10n)

CL Voutsml 0 1p CL1 Voutorg 0 1p CL2 Voutprg 0 1p

XTestSml Vin1 Vin1 Vin1 Vin1 Voutsml Vdd SmlNAND4 XTestOrg Vin1 Vin1 Vin1 Vin1 Voutorg Vdd OrgNAND4 XTestPrg Vin1 Vin1 Vin1 Vin1 Voutprg Vdd PrgNAND4

.SUBCKT SmlNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.75u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.75u L=0.25u MN3   3    In3   2   0     CMOSN W=1.75u L=0.25u MN2   2    In2   1   0     CMOSN W=1.75u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; SmlNAND4
 * Subcircuit Definitions                                  *
 * Subcircuit Definitions                                  *

.SUBCKT PrgNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.75u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.00u L=0.25u MN3   3    In3   2   0     CMOSN W=1.25u L=0.25u MN2   2    In2   1   0     CMOSN W=1.50u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; PrgNAND4

.SUBCKT OrgNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.25u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.25u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.25u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.25u L=0.25u MN4   Out  In4   3   0     CMOSN W=4u L=0.25u MN3   3    In3   2   0     CMOSN W=4u L=0.25u MN2   2    In2   1   0     CMOSN W=4u L=0.25u MN1   1    In1   0   0     CMOSN W=4u L=0.25u .ENDS ; OrgNAND4

.PRINT DC I(CL) I(CL1) I(CL2) .DC Vin 0 2.5 0.001 .probe .OP
 * .TRAN   20p 40n 0 10p
 * print_step final_time (results_delay) (step_ceiling)
 * The last two parameters are officially optional,
 * but I recommend that you specify a step_ceiling no
 * greater than the smaller of final_time/1000 or (rise or fall time)/10.

.MODEL CMOSN NMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.4317311 + PHI    = 0.7             VTO    = 0.4238252       DELTA  = 0 + UO     = 425.6466519     ETA    = 0               THETA  = 0.1754054 + KP     = 2.501048E-4     VMAX   = 8.287851E4      KAPPA  = 0.1686779 + RSH    = 4.062439E-3     NFS    = 1E12            TPG    = 1 + XJ     = 3E-7            LD     = 3.162278E-11    WD     = 1.232881E-8 + CGDO   = 6.2E-10         CGSO   = 6.2E-10         CGBO   = 1E-10 + CJ     = 1.81211E-3      PB     = 0.5             MJ     = 0.3282553 + CJSW   = 5.341337E-10    MJSW   = 0.5             )
 * FET Model Parameters                                                     *
 * From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt    *
 * TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring   *
 * DEV: N3740/10    * Temp= 27                                              *
 * DEV: N3740/10    * Temp= 27                                              *

.MODEL CMOSP PMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.6348369 + PHI    = 0.7             VTO    = -0.5536085      DELTA  = 0 + UO     = 250             ETA    = 0               THETA  = 0.1573195 + KP     = 5.194153E-5     VMAX   = 2.295325E5      KAPPA  = 0.7448494 + RSH    = 30.0776952      NFS    = 1E12            TPG    = -1 + XJ     = 2E-7            LD     = 9.968346E-13    WD     = 5.475113E-9 + CGDO   = 6.66E-10        CGSO   = 6.66E-10        CGBO   = 1E-10 + CJ     = 1.893569E-3     PB     = 0.9906013       MJ     = 0.4664287 + CJSW   = 3.625544E-10    MJSW   = 0.5             )

.end code