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=CMOS AND Gates Design Project - Group 13= Project wiki URL: http://02-13ee307w08.wikispaces.com Amanda Grannen (smeets126 at yahoo.com), Chiweng Kam (ckam at calpoly.edu) Marc Tapalla (marc.tapalla at gmail.com), Kalvin Vu (kalvinvu at gmail.com)

In this project, we analyzed and compared three different 8-input AND gates in terms of speed, power dissipation, and transistor area. Using a figure of merit (the product of those three characteristics), we determined the optimal AND gate design out of the three. Additionally, using MoHAT and circuit design techniques learned in EE307, we designed our own AND gate to achieve a better figure of merit.

[|EE 307 Project Wiki] - A wiki page for EE 307 Project. [|EE 307 Course Link] - This link provides some old project page. [|CMOS AND Gate Project] - This webpage contains the details and the requirements for the project. It also includes the PSpice code.

Summary of the CMOS AND Gates Analysis
(ns*mW*µm²) || 36.78 || 12.00 || 35.53 || 7.600 || NMOS: W= 4 L=.25 || For NAND4 gates: PMOS: W= .25 L=.25 NMOS: W= 4 L=.25
 * || Big Two-Level || Medium Two-Level || Four Level || Optimized Med. Two-Level ||
 * Speed (ns) || 1.428 || 1.255 || 0.7998 || 1.193 ||
 * Avg. Power (mW) || 0.7465 || 0.7080 || 1.154 || 0.6870 ||
 * Area (µm²) || 34.5 || 13.5 || 38.5 || 9.25 ||
 * Figure of Merit
 * Trans. Sizes (µm) || PMOS: W=.25 L=.25

For NOR2x4 Gate: PMOS: W= 8 L=.25 NMOS: W=2 L=.25 || For NAND2 gates: PMOS: W=.25 L=.25 NMOS: W=1 L=.25

For NOR2x4 Gate: PMOS: W=8 L= .25 NMOS: W=2 L= .25

For NAND2x16 gate: PMOS: W=4 L=.25 NMOS: W=16 L=.25 || For NAND4 gates: PMOS: W=.75 L=.25 NMOS4: W=1 L=.25 NMOS3: W=1.25 L=.25 NMOS2: W=1.5 L=.25 NMOS1: W=1.75 L=.25

For NOR2x4 Gate: PMOS: W=8 L=.25 NMOS: W=2 L=.25 || We found that the medium two-level gate had the best figure of merit with the lowest power dissipation and area, but not propagation delay. This urged us to use it as a base for our custom design gate.

Propagation Delay
By definition, propagation delay is the time it takes for the output voltage to react to changes to the input voltage. We measured this by finding the time starting where the input voltage reaches the midpoint of the total voltage (1.25V) and ending where the output voltage reaches the midpoint. We performed this measurement for both rise and fall phases and then averaged to find the total propagation delay. The following diagram (click to see full plot) illustrated an example measurement.
 * Figure 1**: An example measurement for Propagation Delay.

Power
By taking into account the input, output, and supply voltages/currents in each gate, we can measure the average power dissipation. We then let the simulation run until the average power levels out (change by <1% from one period to the next). The following shows the PSpice Code for this measurement. code AVG(-V(Vdd)*I(Vdd)-I(Vin)*V(Vin1)+V(52)* I(Cout2))

code

Area
Depending on the circuit, we used transistors with different sizes (based on the given PSpice code). Find out the detailed area for the transistors for each AND gates here. Basically, we calculated the transistor area by multiplying the width(W) and the length(L).

Design Analysis, Design Idea and Design Process
1. After the comparison of the three circuits, we found that the medium two-level circuit has significantly low FOM. As a result, we decided to optimize this medium two-level circuit for our custom AND gate design.

2. Due to the lower carrier mobility of holes, PMOS stack series is slower than an NMOS stack series. Therefore, NAND implementation is more preferable in a fast circuit design than NOR implementation. Our first attempt is to replace the 2-input NOR gate with three inverters and a 2-input NAND. However, under 1MHz, it required very strong PMOS pull-up transistors in the three inverters in order to obtain rail-to-rail logics. This means that the size of three inverters will have to be big. At the end, this attempt didn’t decrease the FOM because of the increase of area compared to the original medium two-level circuit.

3. The other way to optimize the original circuit is to adjust the W/L ratio of the NAND gate. Using the MoHAT circuit analysis as following, we can see how W/L ratio can affect the VTC [1]. To simplify the analysis, we used a two-input NAND gate instead of the four-input NAND gate. We performed the analysis for the worst case situation when Vin = Vout = VM since the maximum current flows through the gate at VM.


 * Assume both the PMOS and NMOS devices have the same conduction parameter kN and kP. Ignore the body effect of MN2 for simplification.

To calculate the gate threshold voltage: Vin = Vout = VM


 * Hypothesis:** MP1, MP3, MN2 Saturation and MN1 Linear

With current through SAT MN1 and LIN MN2 (when Vin = Vout = VM), we can find the current through the NMOS: IDN = kN(VM – VDS1 – VTN)^2 ...................................................(1) IDN = kN[2(VM – VTN)VDS1 – VDS1^2] .......................................(2)
 * Analysis: **

Also, current goes through the MP1 and MP2 with the current relationship: 2IDP = IDN ................................................................................(3)

And the current through the SAT MP1 and MP2 is IDP = kp(VDD – VM + VTP)^2 .....................................................(4)

Combining equations (1),(2),(3) and (4), we have



The resulting equation for VM shows that the ratio of kp/kN can directly affect the value of VM. Meanwhile, the W/L of the transistors affect the ratio of kP/kN according to the relationship:



Assume VTN = 0.4238, VTP = - 0.5536, µP/ µN = 4.82 and VDD = 2.5V First with (W/L)p = 1 and (W/L)N = 16

Test: MP1, MP3, MN2 Saturation and MN1 Linear ..............(Check)

Similarly, with (W/L)p = 3.0 and (W/L)N = 7.0, we have VM = 1.553V Test: MP1, MP3, MN2 Saturation and MN1 Linear ..............(Check) || ||

4. As seen in the MoHAT analysis above, by increasing the ratio of (W/L)P over (W/L­)N, we can increase the gate threshold voltage VM. As long as we maintained the noise margin, larger VM is desirable because large VM increase the current flow during the logic switch. For CMOS gate with, this means a better propagation delay and faster circuit.

5. Based on the previous analysis, we increased the ratio of (W/L)P over (W/L)N of the original circuit and also decreased the size of the NMOS significantly. Table I shows the result of the adjustment (the two Columns for the Original NAND gate and Small NAND gate). As expected, the value of VM increased from 0.806V to 1.303V whereas the VTC shifted to the right in Figure 2. Also, the noise margin and transition width were within reasonable range.

6. To further improve our custom NAND gate, we applied the transistor sizing technique to modify the W/L ratio for the NMOS. The progressive sizing technique entails that the pull up circuit elements (PMOS) all have the same W/L ratio. The pull down circuit elements (NMOS) get increasingly larger as you move closer to ground. The reason for this is that each NMOS must be able to carry the discharge current of the NMOS located in between itself and the output. As you move closer to ground, there is more discharge current to carry; therefore, a larger NMOS is appropriate. This sizing technique also keeps the diffusion capacitance contribution to the output capacitor small. With PGate = PDC + PAC = fCLVDD^2 for CMOS gate, reducing CL means the reduction of both propagation delay and power dissipation.

7. Going off this theory, we decreased the size of the first NMOS to have a W/L ratio of 1µ/.25µ. From there, we added 0.25µ to the width with each NMOS until ground. The four values were now 1µ/.25µ, 1.25µ/.25µ, 1.5µ/.25µ, 1.75µ/.25µ. Another important feature to consider was the size of the PMOS, although we did want to keep them all at the same ratio, we decided to increase their size for provide for a stronger PMOS and larger ratio of (W/L)P over (W/L)N. We increased it to .75µ/.25µ

Table I also shows the comparison between the small NAND gate and the Progressive NAND gate. The progressive sizing technique further increased our VM from 1.303V to 1.387V while maintaining reasonable noise margin. In Figure 2, the VTC with progressive sizing shifted further to the right.

**Table I**: the comparison between different 4-input NAND Gate with different W/L ratio configuration. ||< Small NAND Gate ||< Progressive NAND || PMOS: W= .25 L=.25 NMOS: W= 4 L=.25 ||< PMOS: W=.75 L=.25 NMOS: W=1.75 L=.25
 * < ||< Original NAND Gate
 * < VIH ||< 0.9080 ||< 1.536 ||< 1.634 ||
 * < VIL ||< 0.5400 ||< 1.136 ||< 1.240 ||
 * < VM ||< 0.8060 ||< 1.303 ||< 1.387 ||
 * < NMH ||< 1.592 ||< 0.9644 ||< 0.8660 ||
 * < NML ||< 0.5400 ||< 1.136 ||< 1.240 ||
 * < Transition Width ||< 0.368 ||< 0.400 ||< 0.394 ||

||< PMOS: W=.75 L=.25 NMOS4: W=1 L=25 NMOS3: W=1.25 L=.25 NMOS2: W=1.5 L=.25 NMOS1: W=1.75 L=.25 ||
 * < (W/L)p ||< 1.0 ||< 3.0 ||< 3.0 ||
 * < (W/L)N ||< 16.0 ||< 7.0 ||< 4.0 / 5.0 / 6.0/ 7.0 ||
 * < Size (um) ||< 5.0 ||< 2.5 ||< 2.125 ||



7. Finally, we modified the original medium two level AND gate design with our two optimized 4-input NAND gate design. Through analysis of the graphs created, we found a new **average propagation delay of 1.1925ns.**

8. We also measured the average power dissipation over a significant amount of time. Using the PSpice cursors on the following graph, we found **average power dissipation to be 0.687mW.**

9. Table II and Table III summarized the calculation for the area of the gate.

Total are for both NAND gates is 2(2.125) = 4.25um²
 * Table II**: The area for the 2 NAND gates (4 PMOS and 4 NMOS each)
 * || W (um) || L (um) || Area (um²) ||
 * PMOS || .75 || .25 || .1875 ||
 * NMOS4 || 1 || .25 || .25 ||
 * NMOS3 || 1.25 || .25 || .3125 ||
 * NMOS2 || 1.5 || .25 || .375 ||
 * NMOS1 || 1.75 || .25 || .4375 ||

Total area for NOR gate is 2(2.5) = 5um²
 * Tabel III**: The area for the NOR gate
 * || W (um) || L (um) || Area (um²) ||
 * PMOS || 8 || .25 || 2 ||
 * NMOS || 2 || .25 || .5 ||

Total area for entire circuit is 4.25 + 5 = **9.25um²**

9. Using these three values (prop delay, average power and area), we can solve for the figure of merit.
 * Figure of Merit = Prop Delay x Area x Avg Power = 1.1965ns x 0.687mW x 9.25um² = 7.600**

This value is 35% better than the original circuit which had a FOM of 12.00

10. Lastly, we measured the noise margin for the custom circuit as shown in Figure 3 in order to verify if our design meets the noise margin requirement of at least 0.25V. It proves that the custom AND gate indeed met the design requirement.

**Voltage/Power Characteristics**
Note: click on each plots for full size view

**Modified Medium Two-Level AND Gate**
NMH = VOH – VIH = 2.5V – 1.2175 = 1.2825V NML = VIL – VOL = 1.3234V – 0V = 1.3234V ||
 * In/Out Voltage || [[image:modmedinout.JPG width="542" height="109" link="http://02-13ee307w08.wikispaces.com/space/showimage/modmedinout.JPG"]] ||
 * Power || [[image:modmedpower.JPG width="537" height="100" link="http://02-13ee307w08.wikispaces.com/space/showimage/modmedpower.JPG"]] ||
 * Noise Margins || [[image:noisemarg.JPG width="542" height="109" link="http://02-13ee307w08.wikispaces.com/space/showimage/noisemarg.JPG"]]
 * Figure 3**: The PSpice Simulation for the modified medium two-level AND Gate.

**Big Two-Level AND Gate**

 * In/Out Voltage || [[image:biginout.JPG width="538" height="113" link="http://02-13ee307w08.wikispaces.com/space/showimage/biginout.JPG"]] ||
 * Power || [[image:bigpower.JPG width="540" height="111" link="http://02-13ee307w08.wikispaces.com/space/showimage/bigpower.JPG"]] ||
 * Figure 4**: The PSpice Simulation for the big two-level AND gate.

**Medium Two-Level AND Gate**

 * In/Out Voltage || [[image:medinout.JPG width="537" height="100" link="http://02-13ee307w08.wikispaces.com/space/showimage/medinout.JPG"]] ||
 * Power || [[image:medpower.JPG width="537" height="104" link="http://02-13ee307w08.wikispaces.com/space/showimage/medpower.JPG"]] ||
 * Figure 5**: The PSpice Simulation for the medium two-level AND gate.

**Four Level AND Gate**

 * In/Out Voltage || [[image:fourinout.JPG width="542" height="109" link="http://02-13ee307w08.wikispaces.com/space/showimage/fourinout.JPG"]] ||
 * Power || [[image:fourpower.JPG width="537" height="100" link="http://02-13ee307w08.wikispaces.com/space/showimage/fourpower.JPG"]] ||
 * Figure 6****:** The PSpice Simulation for the four level AND gate

Modified Medium Two-Level AND Gate
code Xupper Vin1 Vin1 Vin1 Vin1 Upper_out Vdd MODNAND4 Xlower Vin1 Vin1 Vin1 Vin1 Lower_out Vdd MODNAND4 Xnor   Upper_out Lower_out 52 Vdd MODNOR2x4 Cout2  52   0     1p
 * Medium Two-Level AND Gate Figures 2,5
 * All inputs (1-8) tied together
 * All inputs (1-8) tied together

.SUBCKT MODNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.00u L=0.25u MN3   3    In3   2   0     CMOSN W=1.25u L=0.25u MN2   2    In2   1   0     CMOSN W=1.50u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; MODNAND4

.SUBCKT MODNOR2x4 In1 In2 Out Vdd MP1   Out   In1   1   Vdd    CMOSP W=8u L=0.25u MP2     1   In2 Vdd   Vdd    CMOSP W=8u L=0.25u MN2   Out   In2   0     0    CMOSN W=2u L=0.25u MN1   Out   In1   0     0    CMOSN W=2u L=0.25u .ENDS ; NOR2x4 code







Click here to see circuit layout and PSpice code given for the other gates. Also includes transistor definitions for each sub-gate.

Extra Credit Simulation Codes
code Vdd   Vdd    0    2.5
 * EE 307 CMOS AND Gate Project Winter 2008
 * Rails

VI1 Vin1 0 PULSE (2.5 0 0 0.5n 0.5n 5n 10n) VI2 Vin2 0 PULSE (2.5 0 0 0.5n 0.5n 10n 20n) VI3 Vin3 0 PULSE (2.5 0 0 0.5n 0.5n 20n 40n) VI4 Vin4 0 PULSE (2.5 0 0 0.5n 0.5n 40n 80n) VI5 Vin5 0 PULSE (2.5 0 0 0.5n 0.5n 80n 160n) VI6 Vin6 0 PULSE (2.5 0 0 0.5n 0.5n 160n 320n) VI7 Vin7 0 PULSE (2.5 0 0 0.5n 0.5n 320n 640n) VI8 Vin8 0 PULSE (2.5 0 0 0.5n 0.5n 640n 1280n)

Xupper Vin1 Vin2 Vin3 Vin4 Upper_out Vdd MODNAND4 Xlower Vin5 Vin6 Vin7 Vin8 Lower_out Vdd MODNAND4 Xnor   Upper_out Lower_out 52 Vdd MODNOR2x4 Cout2  52   0     1p
 * Medium Two-Level AND Gate Figures 2,5
 * All inputs (1-8) tied together
 * All inputs (1-8) tied together

.SUBCKT MODNAND4 In1 In2 In3 In4 Out Vdd MP1   Out  In1 Vdd Vdd     CMOSP W=0.75u L=0.25u MP2   Out  In2 Vdd Vdd     CMOSP W=0.75u L=0.25u MP3   Out  In3 Vdd Vdd     CMOSP W=0.75u L=0.25u MP4   Out  In4 Vdd Vdd     CMOSP W=0.75u L=0.25u MN4   Out  In4   3   0     CMOSN W=1.00u L=0.25u MN3   3    In3   2   0     CMOSN W=1.25u L=0.25u MN2   2    In2   1   0     CMOSN W=1.50u L=0.25u MN1   1    In1   0   0     CMOSN W=1.75u L=0.25u .ENDS ; MODNAND4
 * Subcircuit Definitions                                  *
 * Subcircuit Definitions                                  *

.SUBCKT MODNOR2x4 In1 In2 Out Vdd MP1   Out   In1   1   Vdd    CMOSP W=8u L=0.25u MP2     1   In2 Vdd   Vdd    CMOSP W=8u L=0.25u MN2   Out   In2   0     0    CMOSN W=2u L=0.25u MN1   Out   In1   0     0    CMOSN W=2u L=0.25u .ENDS ; NOR2x4


 * End Subcircuit Definitions                              *
 * End Subcircuit Definitions                              *

.TRAN   20n 1280n 0 1.28n .probe .OP
 * print_step final_time (results_delay) (step_ceiling)
 * The last two parameters are officially optional,
 * but I recommend that you specify a step_ceiling no
 * greater than the smaller of final_time/1000 or (rise or fall time)/10.
 * .DC Vin 0 2.5 0.001

.MODEL CMOSN NMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.4317311 + PHI    = 0.7             VTO    = 0.4238252       DELTA  = 0 + UO     = 425.6466519     ETA    = 0               THETA  = 0.1754054 + KP     = 2.501048E-4     VMAX   = 8.287851E4      KAPPA  = 0.1686779 + RSH    = 4.062439E-3     NFS    = 1E12            TPG    = 1 + XJ     = 3E-7            LD     = 3.162278E-11    WD     = 1.232881E-8 + CGDO   = 6.2E-10         CGSO   = 6.2E-10         CGBO   = 1E-10 + CJ     = 1.81211E-3      PB     = 0.5             MJ     = 0.3282553 + CJSW   = 5.341337E-10    MJSW   = 0.5             )
 * FET Model Parameters                                                     *
 * From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt    *
 * TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring   *
 * DEV: N3740/10    * Temp= 27                                              *
 * DEV: N3740/10    * Temp= 27                                              *

.MODEL CMOSP PMOS (                                LEVEL  = 3 + TOX    = 5.7E-9          NSUB   = 1E17            GAMMA  = 0.6348369 + PHI    = 0.7             VTO    = -0.5536085      DELTA  = 0 + UO     = 250             ETA    = 0               THETA  = 0.1573195 + KP     = 5.194153E-5     VMAX   = 2.295325E5      KAPPA  = 0.7448494 + RSH    = 30.0776952      NFS    = 1E12            TPG    = -1 + XJ     = 2E-7            LD     = 9.968346E-13    WD     = 5.475113E-9 + CGDO   = 6.66E-10        CGSO   = 6.66E-10        CGBO   = 1E-10 + CJ     = 1.893569E-3     PB     = 0.9906013       MJ     = 0.4664287 + CJSW   = 3.625544E-10    MJSW   = 0.5             )

.end code







As seen from the simulations, the power dissipation of the custom gate running with a 100 MHz 8-bit counter as the input (as opposed to the input as the same 100 MHz square wave applied to each input) is nearly zero. With the inputs all connecting together to a pulse and the pulse switches from logic high to logic low, the maximum possible amount of current the circuit can draw flows through the circuit. As a result, we observe a reasonable amount of average power dissipation when we tied all the input to a single pulse.
 * Explanation and Observation:**

In the case where we applied an 8-bit counter to the eight inputs, the different inputs are either high or low, only in one instance when the gate have all logic high inputs and made the transition to output logic low. More specifically, input 1 of the custom gate switches between high and low throughout the transient simulation—but as a complementary input 8 is low for half of the time range of the transient analysis. It thus prevented a lot of current flow for most of time. By taking the average over a long period, this allows the 8-bit counter inputs has an average power dissipation of nearly zero watts.

Reference
[1] Gopalan, K.G. //Introduction to Digital Microelectronic Circuits//, Irwin: McGraw Hill Higher Education, 2005. Page: 392-397 [2] Mary Jane Irwin & Vijay Narayanan, //CSE477 VLSL Digital Circuits Fall 2003, Lecture Slides//, [Online]. Available: http://mdlwiki.cse.psu.edu/twiki/pub/MDL/MJ1477/cse477-11speed.ppt, Slides 8-9, 14-15 [Accessed: Febrary 29, 2008]